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RustSTA

RustSTA analyzes gate-level Verilog, Liberty, SDC and SPEF with persistent multi-corner timing results, bounded queries and incremental updates.

All RustEDA modules

Timing feedback for the next design iteration.

Development update · 2026-11-01

The source now includes mixed standard-cell/SRAM Liberty conventions, explicit global early/late timing derates and driving-cell waveforms on extracted and propagated-clock paths. RC preparation runs independent nodes within each graph level on a bounded rayon pool, then commits results in topological order. The memory estimate includes an additional 184 bytes per node for jobs/results.

Source, evidence and remaining limits

Development status · 2026-10-28

RustSTA 0.4.3 adds non-tree extracted RC networks to the integrated timing flow. SPEF import, effective-capacitance waveforms and propagated primary clocks are supported. Dual-PDK reference/circuit checks accompany full/incremental and CPU/CUDA consistency checks. Mixed-library SRAM timing and global derates remain experimental work outside this snapshot.

Progress, measured agreement and known residuals →

Analyze. Trace. Iterate.

Run multi-corner static timing analysis, keep the result as an immutable revision, then inspect the paths and endpoints that need attention. Queries read the memory-mapped timing store without rerunning propagation.

ruststa run --workspace ./ws --base-rev rev1 --max-paths 5 --format json
ruststa report --workspace ./ws --rev rev2 --section summary --format json
ruststa path --workspace ./ws --rev rev2 --target path1 --format json

Start with the bundled design or import your own netlist.

A CLI you can compose

  • Follow the critical path.

    Analyze setup, hold, recovery, removal, latches and clock gating. Trace a path, inspect a pin, or filter endpoint reports.

    Timing workflow →

  • Give agents a contract.

    JSON on stdout, coded diagnostics on stderr, shell-safe handles, and explicit revision guards for every update to an existing workspace.

    Agent integration →

  • Keep the computation predictable.

    Deterministic CPU reference propagation in f64. Optional native CUDA. Explicit path and propagation-state budgets.

    Backends and precision →

  • Inspect the evidence.

    Separate checker and full rerun modes, analytic fixtures, incremental consistency checks, and pinned Sky130 and GF180 libraries.

    Verification scope →

From source to a timing report

Step Input Result
Import Structural Verilog, Liberty, SDC A design revision with compiled input tables
Analyze An explicit base revision and operating corners sta.rbin, summary and ranked paths
Inspect A revision, path handle or endpoint filter JSON or text reports without another analysis
Check The stored result and a verification method sta_check.json with explicit status and diagnostics

The default CPU build needs no GPU or Python runtime. The quickstart uses checked-in synthetic inputs and shows the complete import → analysis → report → check flow.

Choose your path

I want to… Start here
Build the tools and analyze a small design Installation → quickstart
Analyze my own netlist across corners Timing workflow → supported scope
Drive timing from an agent or CI Agent guide → CLI → reports
Assess correctness and verification limits Checking → evidence
Measure runtime or choose CPU/CUDA Performance → backends
Contribute to RustSTA Architecture → contributing

Analysis scope

RustSTA 0.4.3 is a source preview. It supports ideal and explicitly propagated primary clocks, ideal/lumped wires and detailed SPEF RC networks. Generated clocks, CPPR, CCS and crosstalk remain outside scope. The independent checker returns undecided for extracted RC; full recomputation checks consistency. Check the support table before interpreting a result.

Part of the RustEDA tool family. Use RustSys to synthesize RTL to standard cells, then analyze the exported structural netlist with RustSTA.