DESIGN. MEASURE. IMPROVE.

Infrastructure for chip-design self-improvement

Shorten the work between inference steps.

RustEDA connects native synthesis, timing and physical design with a revisioned workspace. An agent proposes RTL. Tools implement and verify it. Measured feedback guides the next iteration.

Start building Explore the modules

Ibex SG13G2 / EZ130

The latest two recorded native runs complete 129/129 steps and all 16 gates in 472.2 s and 472.6 s, using EZ130 cells and two real IHP SRAM macros. SRAM-preserving synthesis, mixed-library timing, spacing-aware placement and a pinned early signoff schedule are now captured in the development sources. The older matched LibreLane run failed foundry main DRC; no cross-tool ratio is published for these newer native-only measurements.

Latest Ibex campaign → · Engine capabilities →

Build the feedback loop

• Synthesize

  RTL, mapped cells and equivalence checks.

  RustSys →

• Analyze timing

  Constraints, parasitics and critical paths.

  RustSTA →

• Implement

  Placement, routing, extraction and GDS.

  RustROAD →

• Simulate circuits

  Differentiable SPICE waveforms and adjoint gradients.

  RustSpice →

• Run and recover

  Bounded execution and verified checkpoints.

  Run a flow →

• Inspect and act

  Shared views, paths and revision-bound selections.

  Open the workbench →

• Share a foundation

  Models, formats, disk workspaces and compute.

  RustEDA Common →

Faster tools. Faster iterations.

Chip-design RSI means iterating on a design using verified feedback. Accelerating the work outside model inference improves the whole iteration only in proportion to the time that work consumes. Amdahl's law makes that limit explicit.

Time spent in tools

80%

Aggregate tool speedup

10×

3.57×

illustrative iteration speedup

1 / ((1 − f) + f / s). This is a model, not a measured RustEDA result.

Read the measurement scope · Check current qualification