RTL-to-GDS closeout (2026-10-25)¶
The 16 baseline design/PDK pairs satisfy the gate: 15 passed,
1 deviation_declared, zero failed and zero unverified.
Every row was run from the clean qualification commit 1f86687baaf7e6753addb9351b83f3561fd714f4, with the
full deterministic rebuild, negative controls and artifact binding enabled.
Evidence: rtl2gds-closeout-2026-10-25.json.
| Design | SKY130 | GF180 |
|---|---|---|
| pipeline | passed | passed |
| dense | passed | passed |
| counter | passed | passed |
| uart_tx | passed | passed |
| alu | passed | passed |
| fifo | deviation_declared | passed |
| regfile | passed | passed |
| mult | passed | passed |
Changes and acceptance¶
- GF180 DRV closure now co-sizes drivers/buffers, protects hold paths and has bounded additional candidate/layout work. The 1.0 ns maximum-transition limit and the frozen pre-layout clock-period rule remain unchanged.
- The MPW declaration policy keeps the raw original error, brackets a reference driver-waveform step and requires raw agreement within 0.2 ps at a nearby sample across it, plus an independent transistor/RC vote. It never relaxes endpoint parity. Failed and incomplete proofs remain failures.
- The mult declaration experiment was rejected by that policy. Its physical clock-leaf fanout was reduced from eight to four, as was regfile/SKY130's, reducing loading and restoring ordinary timing/annotation acceptance. Their SDCs and periods are unchanged; no special timing waiver is used for them.
- Hold-cell removal is not always a fault after other cells were resized. A removal that both engines prove still meets hold is recorded, and a separate explicit 2 ns hold-uncertainty fault must be rejected by both. Real misses and incomplete comparisons continue to fail the control gate.
- Installed tool locations, current Verilator's public JSON interface, GNU time discovery and inherited memory limits are handled explicitly. Original tool identities are retained; current results were regenerated with the qualified tools. SERV provenance now distinguishes its Apache-2.0 decoder from ISC files.
Endpoint parity stayed gated at the unchanged 1 ps limit. The three parallel runners were confined to an 8 GiB RAM / 2 GiB swap cgroup with a finite wall-clock guard. The raw receipts are in the evidence file above.
Validation also includes 137 local Python tests and the corresponding CI, plus the root integration and RustSTA scope/safety checks documented in the RustEDA superproject. The implementation identity and original branch are retained in the raw receipts.
Limits¶
This is block-level qualification, not foundry tapeout signoff. Density is reported separately; IR/EM, SI, OCV/CPPR, fill, pad/seal structures and industrial scale are not newly verified here. OpenC910 checker reproduction still lacks its original raw case; full GF180 latch timing and high-R Ceff remain explicit limits. Independent legal, foundry and engineering reviews are not self-certified. The superproject publishes the current scope and limitations. Original review and decision records are preserved locally.